The present invention relates to a memory circuit and more particularly to a static type ciruit provided with an internal control signal generator for generating timing signals when at least one input signal changes in level.
As static type memory circuits, so-called internally synchronous type memory have been majorly employed because they consume less amount of power consumption. The internally synchronous type memory has a timing signal generater which generates a series of timing signals for controlling the respective functional circuits in the memory upon each change in at least one input signal such as address input signals.
In order to further reducing the power consumption and increasing the memory capacity, there has been proposed a so-called pulse-word architecture in which after data stored in a selected memory cell is read and amplified by a sense amplifier and the amplified data by the sense amplifier is held by a latch circuit for producing a read-out signal, a word line decoder and the sense amplifier are reset. Thus, the power consumption caused by the word line decoder and the sense amplifier is avoided while the read-out signal is generated by the latch circuit.
The pulse word architecture suppresses undesired charge and discharge currents in bit lines and in data bus lines as well as DC current of the sense amplifier, and is effective for decreasing the consumption of electric power.
In order to realize the pulse word architecture, it is an indispensable requirement to provide the memory circuit with an internal control signal generator which detects a change in address to generate internal timing signals.
The above-mentioned conventional memory circuit has defects as described below.
One of the nuisances involved in the memory circuit is a change in the power source voltage Vcc and in the ground potential GND accompanying a change in the operation current in the memory circuit. Particularly, the output transistor usually charges and discharges a capacity of from several tens to several hundreds of picofarads, and is generally designed to exhibit a large transistor ability. Therefore, the switching current of the output transistor at the time of reading operation causes the power source voltage Vcc and ground potential GND to change most greatly among other circuit operations.
The input stage of an address buffer may sense a change in the power supply voltage Vcc and in the ground potential GND caused by this change as the change in the input potential itself applied thereto, whereby the address buffer starts to operate. That is, the potential change is added to the input voltage of the address buffer, and the input level loses its actual, absolute level which is detrimental to the characteristics. Moreover, a great change in the potential makes it difficult to satisfy the specifications of the input level.